Semiconductor Engineering

Smarter DFT Infrastructure And Automation Emerge As Keys To Managing DFT Design Scaling

The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, ...
Semiconductor Engineering

Smart Plug-And-Play DFT For Arm Cores

Modern SoCs are experiencing continued growth in capabilities and design sizes with more and more subsystem IPs being implemented. These large, complex, multi-core SoCs need strategies for DFT and ...
Electronic Design

DFT Strategies for SOC Designs

Many IC designers finally have embraced design for testability (DFT) in the form of scan insertion for digital circuit designs because of the significant time-to-production advantages these techniques ...
Design-Reuse

A Unified DFT Verification Methodology

In today’s fast growing Systems-on-Chip (SoC), incomplete or ineffective DFT support due to poor specification or loose design practices can quickly become the critical path to making market windows ...
Design-Reuse

How are you planning to verify all that DfT?

As gate counts continue to swell at a rapid pace, modern systems-on-chip (SoCs) are increasingly integrating more design-for-testability (DfT) capabilities 1. Test and diagnosis of complex integrated ...